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gs81302dt06/11/20/38e -500/450/400/350 144mb sigmaquad-ii+ burst of 4 sram 500 mhz?350 mhz 1.8 v v dd 1.8 v or 1.5 v i/o 165-bump bga commercial temp industrial temp rev: 1.00a 7/2011 1/33 ? 2011, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. features ? 2.5 clock latency ? simultaneous read and write sigmaquad? interface ? jedec-standard pinout and package ? dual double data rate interface ? byte write controls sampled at data-in time ? burst of 4 read and write ? dual-range on-die termination (odt) on data (d), byte w rite ( bw ), and clock (k, k ) intputs ? 1.8 v +100/?100 mv core power supply ? 1.5 v or 1.8 v hstl interface ? pipelined read operation ? fully coherent read and write pipelines ? zq pin for programmable output drive strength ? data valid pin (qvld) support ? ieee 1149.1 jtag-compliant boundary scan ? 165-bump, 15 mm x 17 mm, 1 mm bump pitch bga package ? rohs-compliant 165-bump bga package available sigmaquad? family overview the gs81302dt06/11/20/38e are built in compliance with the sigmaquad-ii+ sram pinout standard for separate i/o synchronous srams. they are 150,994,944-bit (144mb) srams. the gs81302dt06/11/20/38e sigmaquad srams are just one element in a family of low power, low voltage hstl i/o srams designed to operate at the speeds needed to implement economical high performance networking systems. clocking and addr essing schemes the gs81302dt06/11/20/38e sigmaquad-ii+ srams are synchronous devices. they employ two input register clock inputs, k and k . k and k are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. because separate i/o sigmaquad-ii+ b4 ra ms always transfer data in four packets, a0 and a1 are internally set to 0 for the first read or write transfer, and automatically incremented by 1 for the next tr ansfers. because the lsbs are tied off internally, the addre ss field of a sigmaquad-ii+ b4 ram is always two address pins less than the advertised index depth (e.g., the 8m x 18 has a 2m addressable index). parameter synopsis -500 -450 -400 -350 tkhkh 2.0 ns 2.2 ns 2.5 ns 2.86 ns tkhqv 0.45 ns 0.45 ns 0.45 ns 0.45 ns
4m x 36 sigmaquad-ii+ sram?top view 1 2 3 4 5 6 7 8 9 10 11 a cq nc/sa (288mb) sa w bw2 k bw1 r sa sa cq b q27 q18 d18 sa bw3 k bw0 sa d17 q17 q8 c d27 q28 d19 v ss sa nc sa v ss d16 q7 d8 d d28 d20 q19 v ss v ss v ss v ss v ss q16 d15 d7 e q29 d29 q20 v ddq v ss v ss v ss v ddq q15 d6 q6 f q30 q21 d21 v ddq v dd v ss v dd v ddq d14 q14 q5 g d30 d22 q22 v ddq v dd v ss v dd v ddq q13 d13 d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j d31 q31 d23 v ddq v dd v ss v dd v ddq d12 q4 d4 k q32 d32 q23 v ddq v dd v ss v dd v ddq q12 d3 q3 l q33 q24 d24 v ddq v ss v ss v ss v ddq d11 q11 q2 m d33 q34 d25 v ss v ss v ss v ss v ss d10 q1 d2 n d34 d26 q25 v ss sa sa sa v ss q10 d9 d1 p q35 d35 q26 sa sa qvld sa sa q9 d0 q0 r tdo tck sa sa sa odt sa sa sa tms tdi 11 x 15 bump bga?15 x 17 mm 2 body?1 mm bump pitch notes: 1. bw0 controls writes to d0:d8; bw1 controls writes to d9:d17; bw2 controls writes to d18:d26; bw3 controls writes to d27:d35 2. pin a2 is the expansion address. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 2/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350
8m x 18 sigmaquad-ii+ sram?top view 1 2 3 4 5 6 7 8 9 10 11 a cq sa sa w bw1 k nc/sa (288mb) r sa sa cq b nc q9 d9 sa nc k bw0 sa nc nc q8 c nc nc d10 v ss sa nc sa v ss nc q7 d8 d nc d11 q10 v ss v ss v ss v ss v ss nc nc d7 e nc nc q11 v ddq v ss v ss v ss v ddq nc d6 q6 f nc q12 d12 v ddq v dd v ss v dd v ddq nc nc q5 g nc d13 q13 v ddq v dd v ss v dd v ddq nc nc d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc d14 v ddq v dd v ss v dd v ddq nc q4 d4 k nc nc q14 v ddq v dd v ss v dd v ddq nc d3 q3 l nc q15 d15 v ddq v ss v ss v ss v ddq nc nc q2 m nc nc d16 v ss v ss v ss v ss v ss nc q1 d2 n nc d17 q16 v ss sa sa sa v ss nc nc d1 p nc nc q17 sa sa qvld sa sa nc d0 q0 r tdo tck sa sa sa odt sa sa sa tms tdi 11 x 15 bump bga?15 x 17 mm 2 body?1 mm bump pitch notes: 1. bw0 controls writes to d0:d8. bw1 controls writes to d9:d17. 2. pin a7 is the expansion address. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 3/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350
16m x 9 sigmaquad- ii sram?top view 1 2 3 4 5 6 7 8 9 10 11 a cq sa sa w nc k sa r sa sa cq b nc nc nc sa nc/sa (288mb) k bw0 sa nc nc q4 c nc nc nc v ss sa nc sa v ss nc nc d4 d nc d5 nc v ss v ss v ss v ss v ss nc nc nc e nc nc q5 v ddq v ss v ss v ss v ddq nc d3 q3 f nc nc nc v ddq v dd v ss v dd v ddq nc nc nc g nc d6 q6 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc q2 d2 k nc nc nc v ddq v dd v ss v dd v ddq nc nc nc l nc q7 d7 v ddq v ss v ss v ss v ddq nc nc q1 m nc nc nc v ss v ss v ss v ss v ss nc nc d1 n nc d8 nc v ss sa sa sa v ss nc nc nc p nc nc q8 sa sa qvld sa sa nc d0 q0 r tdo tck sa sa sa odt sa sa sa tms tdi 11 x 15 bump bga?15 x 17 mm 2 body?1 mm bump pitch notes: 1. bw0 controls writes to d0:d8. 2. pin b5 is the expansion address. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 4/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350
16m x 8 sigmaquad- ii sram?top view 1 2 3 4 5 6 7 8 9 10 11 a cq sa sa w nw1 k sa r sa sa cq b nc nc nc sa nc/sa (288mb) k nw0 sa nc nc q3 c nc nc nc v ss sa nc sa v ss nc nc d3 d nc d4 nc v ss v ss v ss v ss v ss nc nc nc e nc nc q4 v ddq v ss v ss v ss v ddq nc d2 q2 f nc nc nc v ddq v dd v ss v dd v ddq nc nc nc g nc d5 q5 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc q1 d1 k nc nc nc v ddq v dd v ss v dd v ddq nc nc nc l nc q6 d6 v ddq v ss v ss v ss v ddq nc nc q0 m nc nc nc v ss v ss v ss v ss v ss nc nc d0 n nc d7 nc v ss sa sa sa v ss nc nc nc p nc nc q7 sa sa qvld sa sa nc nc nc r tdo tck sa sa sa odt sa sa sa tms tdi 11 x 15 bump bga?15 x 17 mm 2 body?1 mm bump pitch notes: 1. nw0 controls writes to d0:d3. nw1 controls writes to d4:d7. 2. pin b5 is the expansion address. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 5/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350
pin description table symbol description type comments sa synchronous address inputs input ? r synchronous read input active low w synchronous write input active low bw0 ? bw3 synchronous byte writes input active low x18/x36 only k input clock input active high k input clock input active low tms test mode select input ? tdi test data input input ? tck test clock input input ? tdo test data output output ? v ref hstl input reference voltage input ? zq output impedance matching input input ? qn synchronous data outputs output ? dn synchronous data inputs input ? d off disable dll when low input active low cq output echo clock output ? cq output echo clock output ? v dd power supply supply 1.8 v nominal v ddq isolated output buffer supply supply 1.5 v or 1.8 v nominal v ss power supply: ground supply ? qvld q valid output output ? odt on-die termination input low = low impedance range high/float = high impedance range nc no connect ? ? notes: 1. nc = not connected to die or any other pin 2. when zq pin is directly connected to v ddq , output impedance is set to minimum value and it cannot be connected to ground or left unconnected. 3. k and k cannot be set to v ref voltage. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 6/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 7/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350 background separate i/o srams, from a syst em architecture point of view, are attractive in applications where alte rnating reads and writes are needed. therefore, the sigmaqua d-ii+ sram interface and truth ta ble are optimized for alternating reads and writes. separate i/ o srams are unpopular in app lications where multiple reads or multiple writes are needed because burst read or write transfers fr om separate i/o srams can cut the ram?s bandwidth in half. alternating read-write operations sigmaquad-ii+ srams follow a few simple rules of operation. - read or write commands issued on one po rt are never allowed to interrupt an operation in progress on the other port. - read or write data transfers in progress may not be interrupted. - r and w high always deselects the ram. - all address, data, and control inputs are sampled on clock edges. in order to enforce these rules, each ram combines present st ate information with command i nputs. see the truth table for details. sigmaquad-ii+ burst of 4 sram ddr read the status of the address input, w , and r pins are sampled by the rising edges of k. w and r high causes chip disable. a low on the read enable pin, r , begins a read cycle. r is always ignored if the previous comm and loaded was a read command. clocking in a high on the read enable pin, r , begins a read port deselect cycle. sigmaquad-ii+ burst of 4 sram ddr write the status of the address input, w , and r pins are sampled by the rising edges of k. w and r high causes chip disable. a low on the write enable pin, w , and a high on the read enable pin, r , begins a write cycle. w is always ignored if the previous command was a write command. data is clocked in by the next rising edge of k, the rising edge of k after that, the next rising edge of k, and finally by the next rising edge of k . special functions byte write and nybble write control byte write enable pins are sampled at the same time that data in is sampled. a high on the byte write enable pin associated wit h a particular byte (e.g., bw0 controls d0?d8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. an y or all of the byte write enable pins may be driven high or low during the data in sample times in a write sequence. each write enable command and write address loaded into the ra m provides the base address for a 4-beat data transfer. the x18 version of the ram, for example, may write 72 bits in associatio n with each address loaded. any 9-bit byte may be masked in any write sequence. nybble write (4-bit) control is implemented on the 8-bit-wide version of the device. for the x8 version of the device, ?nybble write enable? and ? nwx ? may be substituted in all the discussion above.
example x18 ram write sequence using byte write enables data in sample time bw0 bw1 d0?d8 d9?d17 beat 1 0 1 data in don?t care beat 2 1 0 don?t care data in beat 3 0 0 data in data in beat 4 1 0 don?t care data in resulting write operation byte 1 d0?d8 byte 2 d9?d17 byte 1 d0?d8 byte 2 d9?d17 byte 1 d0?d8 byte 2 d9?d17 byte 1 d0?d8 byte 2 d9?d17 written unchanged unchanged written written written unchanged written beat 1 beat 2 beat 3 beat 4 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 8/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 9/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350 flxdrive-ii output driver impedance control hstl i/o sigmaquad-ii+ srams are supplied with programmable impedance output drivers. the zq pin must be connected to v ss via an external resistor, rq, to allow the sram to monitor and adjust its output driver impedance. the value of rq must be 5x the value of the desired ram output impedance. the allowable range of rq to guarantee impeda nce matching continuously is between 175 and 350 . periodic readjustment of the output driver impedance is necessary as th e impedance is affected by drifts in supply voltage and temperature. the sram?s output impeda nce circuitry compensates for drifts in supply voltage and temperature. a clock cycle counter periodi cally triggers an impedance evaluation, resets and coun ts again. each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. the output driver is implemented with discrete binary weighted impedance steps. input termination impedance control these sigmaquad-ii+ srams are supp lied with programmable input termination on data (d), byte write ( bw ), and clock (k, k ) input receivers. the input termination is al ways enabled, and the impedance is program med via the same rq resistor (connected between the zq pin and v ss ) used to program output driver impedance, in conjuction with the odt pin (6r). when the odt pin is tied low, input termination is "strong" (i.e., low impedance), and is nominally equal to rq*0.3 thevenin-equivalent when rq is between 175 ? ? ? ? note: d, bw , k, k inputs should always be driven high or low; they should ne ver be tri-stated (i.e., in a hi gh-z state). if the inputs are tri-stated, the input termination will pull the signal to v ddq /2 (i.e., to the switch point of the diff-amp receiver), which could cause the receiver to enter a meta -stable state, resulting in the r eceiver consuming mo re power than it normally would. this could re sult in the device?s operating currents being higher.
separate i/o sigmaquad ii + b4 sram truth table previous operation a r w current operation d d d d q q q q k (t n-1 ) k (t n ) k (t n ) k (t n ) k (t n ) k (t n+1 ) k (t n+1? ) k (t n+2 ) k (t n+2? ) k (t n+2?) k (t n+3 ) k (t n+3? ) k (t n+4 ) deselect x 1 1 deselect x x ? ? hi-z hi-z ? ? write x 1 x deselect d2 d3 ? ? hi-z hi-z ? ? read x x 1 deselect x x ? ? q2 q3 ? ? deselect v 1 0 write d0 d1 d2 d3 hi-z hi-z ? ? deselect v 0 x read x x ? ? q0 q1 q2 q3 read v x 0 write d0 d1 d2 d3 q2 q3 ? ? write v 0 x read d2 d3 ? ? q0 q1 q2 q3 notes: 1. ?1? = input ?high?; ?0? = input ?low?; ?v? = input ?valid?; ?x? = input ?don?t care? 2. ??? indicates that the input requirement or output state is determined by the next operation. 3. q0, q1, q2, and q3 indicate the first, second, third, and f ourth pieces of output data tr ansferred during read operations. 4. d0, d1, d2, and d3 indicate the first, second, third, and f ourth pieces of input data tr ansferred during write operations. 5. users should not clock in metastable addresses. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 10/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350
byte write clock truth table bw bw bw bw current operation d d d d k (t n+1 ) k (t n+1? ) k (t n+2 ) k (t n+2? ) k (t n ) k (t n+1 ) k (t n+1? ) k (t n+2 ) k (t n+2? ) t t t t write dx stored if bwn = 0 in all four data transfers d0 d2 d3 d4 t f f f write dx stored if bwn = 0 in 1st data transfer only d0 x x x f t f f write dx stored if bwn = 0 in 2nd data transfer only x d1 x x f f t f write dx stored if bwn = 0 in 3rd data transfer only x x d2 x f f f t write dx stored if bwn = 0 in 4th data transfer only x x x d3 f f f f write abort no dx stored in any of the four data transfers x x x x notes: 1. ?1? = input ?high?; ?0? = input ?low?; ?x? = input ?don?t care?; ?t? = input ?true?; ?f? = input ?false?. 2. if one or more bwn = 0, then bw = ?t?, else bw = ?f?. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 11/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350
x36 byte write enable ( bwn ) truth table bw0 bw1 bw2 bw3 d0?d8 d9?d17 d18?d26 d27?d35 1 1 1 1 don?t care don?t care don?t care don?t care 0 1 1 1 data in don?t care don?t care don?t care 1 0 1 1 don?t care data in don?t care don?t care 0 0 1 1 data in data in don?t care don?t care 1 1 0 1 don?t care don?t care data in don?t care 0 1 0 1 data in don?t care data in don?t care 1 0 0 1 don?t care data in data in don?t care 0 0 0 1 data in data in data in don?t care 1 1 1 0 don?t care don?t care don?t care data in 0 1 1 0 data in don?t care don?t care data in 1 0 1 0 don?t care data in don?t care data in 0 0 1 0 data in data in don?t care data in 1 1 0 0 don?t care don?t care data in data in 0 1 0 0 data in don?t care data in data in 1 0 0 0 don?t care data in data in data in 0 0 0 0 data in data in data in data in x18 byte write enable ( bwn ) truth table bw0 bw1 d0?d8 d9?d17 1 1 don?t care don?t care 0 1 data in don?t care 1 0 don?t care data in 0 0 data in data in x09 byte write enable ( bwn ) truth table bw0 d0?d8 1 don?t care 0 data in 1 don?t care 0 data in specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 12/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350
nybble write cl ock truth table nw nw nw nw current operation d d d d k (t n+1 ) k (t n+1? ) k (t n+2 ) k (t n+2? ) k (t n ) k (t n+1 ) k (t n+1? ) k (t n+2 ) k (t n+2? ) t t t t write dx stored if nwn = 0 in all four data transfers d0 d2 d3 d4 t f f f write dx stored if nwn = 0 in 1st data transfer only d0 x x x f t f f write dx stored if nwn = 0 in 2nd data transfer only x d1 x x f f t f write dx stored if nwn = 0 in 3rd data transfer only x x d2 x f f f t write dx stored if nwn = 0 in 4th data transfer only x x x d3 f f f f write abort no dx stored in any of the four data transfers x x x x notes: 1. ?1? = input ?high?; ?0? = input ?low?; ?x? = input ?don?t care?; ?t? = input ?true?; ?f? = input ?false?. 2. if one or more nwn = 0, then nw = ?t?, else nw = ?f?. x8 nybble write enable ( nwn ) truth table nw0 nw1 d0?d3 d4?d7 1 1 don?t care don?t care 0 1 data in don?t care 1 0 don?t care data in 0 0 data in data in specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 13/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 14/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350 state diagram power-up read nop load new read address d count = 0 ddr read d count = d count + 1 write nop load new write address d count = 0 ddr write d count = d count + 1 write read read d count = 2 write d count = 2 read write always always read d count = 2 notes: 1. internal burst counter is fixed as 2-bit linear (i.e., when first address is a0 +0, next internal burst address is a0+1. 2. ?read? refers to read active status with r = low, ?read ? refers to read inactive status with r = high. the same is true for ?write? and ?write ?. 3. read and write state machine can be active simultaneously. 4. state machine control timi ng sequence is controlled by k. read d count = 1 always increment read address write d count = 2 increment write address write d count = 1 always
absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ?0.5 to 2.9 v v ddq voltage in v ddq pins ?0.5 to v dd v v ref voltage in v ref pins ?0.5 to v ddq v v i/o voltage on i/o pins ?0.5 to v ddq +0.5 ( . .) . . . .) note: permanent damage to the device may occur if the absolute maximu m ratings are exceeded. operati on should be restricted to recomm ended operating conditions. exposure to conditi ons exceeding the recommended operating condi tions, for an extended period of time, ma y affect reliability of this component. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 15/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350 recommended oper ating conditions power supplies parameter symbol min. typ. max. unit supply voltage v dd 1.7 1.8 1.9 v i/o supply voltage v ddq 1.4 ? v dd v reference voltage v ref v ddq /2 ? 0.05 ? v ddq /2 + 0.05 v notes: the power supplies need to be powered up simult aneo usly or in the following sequence: v dd , v ddq , v ref , followed by signal inputs. the power down sequence must be the reverse. v ddq must not exceed v dd . for more information, read an1021 sigmaquad and sigmaddr power-up. operating temperature parameter symbol min. typ. max. unit junction temperature (commercial range versions) t j 0 25 85 ) note: * the part numbers of industrial temperature range versions end with the character ?i?. unless otherwise noted, all performanc e specifications quoted are evaluated for worst case in the temperature range marked on the device.
thermal impedance package test pcb substrate ja (c/w) airflow = 0 m/s ja (c/w) airflow = 1 m/s ja (c/w) airflow = 2 m/s jb (c/w) jc (c/w) 165 bga 4-layer 16.4 13.4 12.4 8.6 1.2 notes: 1. thermal impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number. 2. please refer to jedec standard jesd51-6. 3. the characteristics of the test fixture pcb influence reported the rmal characteristics of the device. be advised that a good thermal path to the pcb can result in cooling or heating of the ram depending on pcb temperature. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 16/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350 hstl i/o dc input characteristics parameter symbol min max units notes input reference voltage v ref v ddq /2 ? 0.05 v ddq /2 + 0.05 v ? input high voltage v ih1 v ref + 0.1 v ddq + 0.3 v 1 input low voltage v il1 ?0.3 v ref ? 0.1 v 1 input high voltage v ih2 0.7 * v ddq v ddq + 0.3 v 2,3 input low voltage v il2 ?0.3 0.3 * v ddq v 2,3 notes: 1. parameters apply to k, k , sa, d, r , w , bw during normal operation and jtag boundary scan testing. 2. parameters apply to doff , odt during normal operation an d jtag boundary scan testing. 3. parameters apply to zq during jtag boundary scan testing only. hstl i/o ac input characteristics parameter symbol min max units notes input reference voltage v ref v ddq /2 ? 0.08 v ddq /2 + 0.08 v ? input high voltage v ih1 v ref + 0.2 v ddq + 0.5 v 1,2,3 input low voltage v il1 ?0.5 v ref ? 0.2 v 1,2,3 input high voltage v ih2 v ddq ? 0.2 v ddq + 0.5 v 4,5 input low voltage v il2 ?0.5 0.2 v 4,5 notes: 1. v ih(max) and v il(min) apply for pulse widths less than one-quarter of the cycle time. 2. input rise and fall times must be a minimum of 1 v/ns, and within 10% of each other. 3. parameters apply to k, k , sa, d, r , w , bw during normal operation and jtag boundary scan testing. 4. parameters apply to doff , odt during normal operation an d jtag boundary scan testing. 5. parameters apply to zq during jtag boundary scan testing only.
capacitance o c, f = 1 mh z , v dd = 1.8 v) parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 4 5 pf output capacitance c out v out = 0 v 6 7 pf clock capacitance c clk v in = 0 v 5 6 pf note: this parameter is sample tested. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 17/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350 ac test conditions parameter conditions input high level 1.25 v input low level 0.25 v max. input slew rate 2 v/ns input reference level 0.75 v output reference level v ddq /2 note: test conditions as specified with output loading as shown unl ess otherwise noted. dq vt = 0.75 v 50 rq = 250 (hstl i/o) v ref = 0.75 v ac test load diagram input and output leakage characteristics parameter symbol test conditions min. max input leakage current (except mode pins) i il v in = 0 to v dd ?2 ua 2 ua doff i il doff v in = 0 to v dd ?20 ua 2 ua odt i il odt v in = 0 to v dd ?2 ua 20 ua output leakage current i ol output disable, v out = 0 to v ddq ?2 ua 2 ua (t a = 25
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 18/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350 programmable impedance hstl output driver dc electrical characteristics parameter symbol min. max. units notes output high voltage v oh1 v ddq /2 ? 0.12 v ddq /2 + 0.12 v 1, 3 output low voltage v ol1 v ddq /2 ? 0.12 v ddq /2 + 0.12 v 2, 3 output high voltage v oh2 v ddq ? 0.2 v ddq v 4, 5 output low voltage v ol2 vss 0.2 v 4, 6 notes: 1. i oh = (v ddq /2) / (rq/5) +/? 15% @ v oh = v ddq /2 (for: 175 rq 350 ). 2. i ol = (v ddq /2) / (rq/5) +/? 15% @ v ol = v ddq /2 (for: 175 rq 350 ) . 3. parameter tested with rq = 250 and v ddq = 1.5 v or 1.8 v. 4. 0 rq ? 5. i oh = ?1.0 ma 6. i ol = 1.0 ma
operating currents parameter symbol test conditions -500 -450 -400 -350 notes 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c operating current (x36): dd r i dd v dd = max, i out = 0 ma cycle time t khkh min 1530 ma 1540 ma 1400 ma 1410 ma 1170 ma 1180 ma 1055 ma 1065 ma 2, 3 operating current (x18): dd r i dd v dd = max, i out = 0 ma cycle time t khkh min 1260 ma 1270 ma 1175 ma 1185 ma 1055 ma 1065 ma 940 ma 950 ma 2, 3 operating current (x9): dd r i dd v dd = max, i out = 0 ma cycle time t khkh min 1260 ma 1270 ma 1175 ma 1185 ma 1055 ma 1065 ma 940 ma 950 ma 2, 3 operating current (x8): dd r i dd v dd = max, i out = 0 ma cycle time t khkh min 1260 ma 1270 ma 1175 ma 1185 ma 1055 ma 1065 ma 940 ma 950 ma 2, 3 standby current (nop): dd r i sb1 device deselected, i out = 0 ma, f = max, all inputs 0.2 v or v dd ? 0.2 v 305 ma 315 ma 290 ma 300 ma 275 ma 285 ma 260 ma 270 ma 2, 4 notes: 1. power measured with output pins floating. 2. minimum cycle, i out = 0 ma 3. operating current is calculated with 5 0% read cycles and 50% write cycles. 4. standby current is only after all pending r ead and write burst operations are complete d. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 19/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350
ac electrical characteristics parameter symbol -500 -450 -400 -350 units notes min max min max min max min max clock k, k clock cycle time t khkh 2.0 8.4 2.2 8.4 2.5 8.4 2.86 8.4 ns tk variable t kvar ? 0.15 ? 0.15 ? 0.2 ? 0.2 ns 4 k, k clock high pulse width t khkl 0.4 ? 0.4 ? 0.4 ? 0.4 ? cycle k, k clock low pulse width t klkh 0.4 ? 0.4 ? 0.4 ? 0.4 ? cycle k to k high t kh k h 0.85 ? 0.94 ? 1.06 ? 1.23 ? ns k to k high t k hkh 0.85 ? 0.94 ? 1.06 ? 1.23 ? ns dll lock time t klock 2048 ? 2048 ? 2048 ? 2048 ? cycle 5 k static to dll reset t kreset 30 ? 30 ? 30 ? 30 ? ns output times k, k clock high to data output valid t khqv ? 0.45 ? 0.45 ? 0.45 ? 0.45 ns k, k clock high to data output hold t khqx ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ns k, k clock high to echo clock valid t khcqv ? 0.45 ? 0.45 ? 0.45 ? 0.45 ns k, k clock high to echo clock hold t khcqx ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ns cq, cq high output valid t cqhqv ? 0.15 ? 0.15 ? 0.2 ? 0.23 ns cq, cq high output hold t cqhqx ?0.15 ? ?0.15 ? ?0.2 ? ?0.23 ? ns cq, cq high to qlvd t qvld ?0.15 0.15 ?0.15 0.15 ?0.2 0.2 ?0.23 0.23 ns cq phase distortion t cqh cq h t c q hcqh 0.75 ? 0.85 ? 1.0 ? 1.18 ? ns k clock high to data output high-z t khqz ? 0.45 ? 0.45 ? 0.45 ? 0.45 ns k clock high to data output low-z t khqx1 ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ns setup times address input setup time t avkh 0.25 ? 0.275 ? 0.4 ? 0.4 ? ns 1 control input setup time ( r , w ) t ivkh 0.25 ? 0.275 ? 0.4 ? 0.4 ? ns 2 control input setup time ( bwx ) t ivkh 0.2 ? 0.22 ? 0.28 ? 0.28 ? ns 3 data input setup time t dvkh 0.2 ? 0.22 ? 0.28 ? 0.28 ? ns hold times address input hold time t khax 0.25 ? 0.275 ? 0.4 ? 0.4 ? ns 1 control input hold time ( r , w ) t khix 0.25 ? 0.275 ? 0.4 ? 0.4 ? ns 2 control input hold time ( bwx ) t khix 0.2 ? 0.22 ? 0.28 ? 0.28 ? ns 3 data input hold time t khdx 0.2 ? 0.22 ? 0.28 ? 0.28 ? ns notes: 1. all address inputs must meet the specified setup and hold times for all latching clock edges. 2. control signals are r , w . 3. control signals are bw0 , bw1 and ( bw2 , bw3 for x36). 4. clock phase jitter is the variance from cloc k rising edge to the next expected clock rising edge. 5. v dd slew rate must be less than 0.1 v dc per 50 ns for dll lock retention. dll lock time begins once v dd and input clock are stable. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 20/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 21/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350 read nop cq-based timing diagram read a0 write noop read a1 write noop noop noop noop a0 a1 q0 q0+1 q0+2 q0+3 q1 q1+1 q1+2 q1+3 tcqhqx tcqlqx tcqlqv tcqhqv tqvld tcqlqx tcqhqx tcqhqv tcqlqv tqvld tkhix tivkh tkhix tivkh tkhax tavkh k k addr r w qvld q cq cq
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 22/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350 read-write cq-based timing diagram read a0 write a1 read a2 write a3 noop noop noop a0 a1 a2 a3 d1 d1+1 d1+2 d1+3 d3 d3+1 d3+2 d3+3 q0 q0+1 q0+2 q0+3 q2 q2+1 q2+2 q2+3 tcqlqx tcqlqv tcqhqx tcqhqv tqvld tcqhqx tcqhqv tcqlqx tcqlqv tqvld tkhdx tdvkh tkhdx tdvkh tkhix tivkh tkhix tivkh tkhix tivkh tkhix tivkh tkhax tavkh k k addr r w bw x d qvld q cq cq
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 23/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350 write nop timing diagram write a read no-op write b read no-op no-op no-op no-op a0 a1 d0 d0+1 d0+2 d0+3 d1 d1+1 d1+2 d1+3 tkhdx tdvkh tkhix tivkh tkhix tivkh tkhix tivkh tkhix tivkh tkhax tavkh k k addr r w bwx d
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 24/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350 jtag port operation overview the jtag port on this ram operates in a manner that is compliant with ieee standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as jtag). the jtag port input inte rface levels scale with v dd . the jtag output drivers are powered by v dd . disabling the jtag port it is possible to use this device without utilizing the jtag port. the port is reset at power-up and will remain inactive unles s clocked. tck, tdi, and tms are designed with internal pull-up circuits.to assure normal operation of the ram with the jtag port unused, tck, tdi, and tms may be left floating or tied to either v dd or v ss . tdo should be left unconnected. jtag pin descriptions pin pin name i/o description tck test clock in clocks all tap events. all inputs are captured on the rising edge of tck and all outputs propagate from the fa lling edge of tck. tms test mode select in the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state m achine. an undriven tms input will produce the same result as a logic one input level. tdi test data in in the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed b etween tdi and tdo. the register placed between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to the tap controller state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out out output that is active depending on the state of the tap state machine. output changes in response to the fa lling edge of tck. this is the output side of the serial registers placed between tdi and tdo. note: this device does not have a trst (tap reset) pin. trst is optional in ieee 1149.1. the test-logic-reset state is entered while tms is held high for five rising edges of tck. the tap cont roller is also reset automaticly at power-up. jtag port registers overview the various jtag registers, refered to as tes t access port or ta p registers, are selected (one at a time) via the sequences of 1s and 0s applied to tms as tck is strobed. each of the tap regist ers is a serial shift register that captures serial input data o n the rising edge of tck and pushes serial data out on the next falling edge of tck. when a register is selected, it is placed betwe en the tdi and tdo pins. instruction register the instruction register holds the instructi ons that are executed by the ta p controller when it is moved into the run, test/idl e, or the various data register states. instructions are 3 bits long. th e instruction register can be lo aded when it is placed betwee n the tdi and tdo pins. the instruction register is automatically preloa ded with the idcode instruction at power-up or whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single bit register that can be placed between tdi and tdo. it allows serial test data to be passed th rough the ram?s jtag port to another device in the scan chain with as little delay as possible. boundary scan register the boundary scan register is a collection of flip flops that can be preset by the logic level found on the ram?s input or i/o pin s. the flip flops are then daisy chained togeth er so the levels found can be shifted seri ally out of the jtag port?s tdo pin. the boundary scan register also includes a number of place holder flip fl ops (always set to a logic 1). the relationship between t he device pins and the bits in the boundary scan register is described in the scan order table following. the boundary scan
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 25/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350 register, under the control of the tap contro ller, is loaded with the contents of the rams i/o ring when the controller is in capture-dr state and then is placed between the tdi and tdo pins when the controller is moved to shift-dr state. sample-z, sample/preload and extest instructions can be us ed to activate the boundary scan register. instruction register id code register boundary scan register 012 0 31 30 29 12 0 bypass register tdi tdo tms tck test access port (tap) controller 108 1 0 control signals jtag tap block diagram identification (id) register the id register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction re gister. the code is loaded from a 32-bit on-chip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when th e controller is moved into shift- dr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. id register contents see bsdl model gsi technology jedec vendor id code presence register bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x x x x x x x x x x x x x x x x 0 0 0 1 1 0 1 1 0 0 1 1
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 26/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350 tap controller instruction set overview there are two classes of instructions defined in the standard 114 9.1-1990; the standard (public) instructions, and device speci fic (private) instructions. some public instructions are mandatory for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. the tap on th is device may be used to monitor all inpu t and i/o pads, and can be used to load address, data or control signals into the ram or to preload the i/o buffers. when the tap controller is placed in captur e-ir s tate the two least significant bits of the instruction regi ster are loaded wit h 01. when the controller is moved to the shift-ir state the instruction register is placed between tdi and tdo. in this state the de sired instruction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions , the tap executes newly loaded instruct ions only when the controller is moved to update-ir state. the tap instruction set for this device is listed in the following table. select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 11 1 jtag tap controller state diagram instruction descriptions bypass when the bypass instruction is loaded in the instruction register the bypass regi ster is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the board level scan path to be shortened to facili - tate testing of other devices in the scan path.
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 27/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350 sample/preload sample/preload is a standard 1149.1 mandatory public in struction. when the sample / preload instruction is loaded in the instruction register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the boundary scan register. boundary scan regist er locations are not associated with an input or i/o pin, and are loaded with the default stat e identified in the boundary s can chain table at the end of th is section of the datasheet. beca use the ram clock is independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e. in a metastable state). although allowing the tap to sample metastable inputs w ill not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the taps input data capture set-up plus hold time (tts plus tth) . the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary s can register. moving the contro ller to shift-dr state then places the boundary scan register between the tdi and tdo pins. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instru ction register is loaded with all logic 0s. the extest command does not block or override th e ram?s input pins; therefore, the ram?s internal state is still determined by its input pins. typically, the boundary scan re gister is loaded with the desired pattern of data with the sample/preload command. then the extest command is used to outp ut the boundary scan register?s contents, in parallel, on the ram?s data output drivers on the falling edge of tck when the controller is in the update-ir state. alternately, the boundary scan register may be loaded in parallel using the extest command. when the extest instruc - tion is selected, the sate of all the ram?s input and i/o pins, as well as the default values at scan register locations not as so - ciated with a pin, are transfer red in parallel into the boundary scan regist er on the rising edge of tck in the capture-dr state, the ram?s output pins drive out the value of the boundar y scan register location with which each output pin is associ - ated. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi a nd tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. sample-z if the sample-z instruction is loaded in the instruction register, all ram outputs are forced to an inactiv e drive state (high- z) and the boundary scan register is connected between tdi and t do when the tap controller is moved to the shift-dr state. jtag tap instruction set summary instruction code description notes extest 000 places the boundary scan register between tdi and tdo. 1 idcode 001 preloads id register and places it between tdi and tdo. 1, 2 sample-z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all ram output drivers to high-z. 1 gsi 011 gsi private instruction. 1
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 28/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350 jtag port recommended operating conditions and dc characteristics parameter symbol min. max. unit notes test port input low voltage v ilj ? 0.3 0.3 * v dd v 1 test port input high voltage v ihj 0.7 * v dd v dd +0.3 v 1 tms, tck and tdi input leakage current i inhj ? 300 1 ua 2 tms, tck and tdi input leakage current i inlj ? 1 100 ua 3 tdo output leakage current i olj ? 1 1 ua 4 test port output high voltage v ohj v dd ? 0.2 ? v 5, 6 test port output low voltage v olj ? 0.2 v 5, 7 test port output cmos high v ohjc v dd ? 0.1 ? v 5, 8 test port output cmos low v oljc ? 0.1 v 5, 9 notes: 1. input under/overshoot voltage must be ? 1 v < v i < v ddn +1 v not to exceed 2.9 v maximum, with a pulse width not to exceed 20% ttkc. 2. v ilj ddn 3. 0 v iljn 4. output disable, v out = 0 to v ddn 5. the tdo output driver is served by the v dd supply. 6. i ohj = ? 2 ma 7. i olj = + 2 ma 8. i ohjc = ?100 ua 9. i oljc = +100 ua sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. 1 gsi 101 gsi private instruction. 1 gsi 110 gsi private instruction. 1 bypass 111 places bypass register between tdi and tdo. 1 notes: 1. instruction codes expressed in binary, msb on left, lsb on right. 2. default instruction automatically loaded at power-up and in test-logic-reset state. jtag tap instruction set summary
notes: 1. include scope and jig capacitance. 2. test conditions as shown unless otherwise noted. jtag port ac test conditions parameter conditions input high level v dd ? 0.2 v input low level 0.2 v input slew rate 1 v/ns input reference level v dd /2 output reference level v dd /2 tdo v dd /2 50 30pf * jtag port ac test load * distributed test jig capacitance specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 29/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350 jtag port timing diagram tth tts ttkq tth tts tth tts ttklttkl ttkhttkh ttkcttkc tck tdi tms tdo parallel sram input jtag port ac electri cal characteristics parameter symbol min max unit tck cycle time ttkc 50 ? ns tck low to tdo valid ttkq ? 20 ns tck high pulse width ttkh 20 ? ns tck low pulse width ttkl 20 ? ns tdi & tms set up time tts 10 ? ns tdi & tms hold time tth 10 ? ns
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 30/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350 package dimensions?165-bump fpbga (package e) a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 a1 corner top view a1 corner bottom view 1.0 1.0 10.0 1.0 1.0 14.0 150.05 170.05 a b 0.20(4x) ?0.10 ?0.25 c c a b m m ?0.40~0.60 (165x) c seating plane 0.15 c 0.36~0.46 1.50 max.
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 31/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350 ordering information gsi sigmaquad-ii+ sram org part number 1 type package speed (mhz) t j 2 16m x 8 gs81302dt06e-500 sigmaquad-ii+ sram 165-bump bga 500 c 16m x 8 gs81302dt06e-450 sigmaquad-ii+ sram 165-bump bga 450 c 16m x 8 gs81302dt06e-400 sigmaquad-ii+ sram 165-bump bga 400 c 16m x 8 gs81302dt06e-350 sigmaquad-ii+ sram 165-bump bga 350 c 16m x 8 gs81302dt06e-500i sigmaquad-ii+ sram 165-bump bga 500 i 16m x 8 gs81302dt06e-450i sigmaquad-ii+ sram 165-bump bga 450 i 16m x 8 gs81302dt06e-400i sigmaquad-ii+ sram 165-bump bga 400 i 16m x 8 gs81302dt06e-350i sigmaquad-ii+ sram 165-bump bga 350 i 16m x 8 gs81302dt06ge-500 sigmaquad-ii+ sram rohs-compliant 165-bump bga 500 c 16m x 8 gs81302dt06ge-450 sigmaquad-ii+ sram rohs-compliant 165-bump bga 450 c 16m x 8 gs81302dt06ge-400 sigmaquad-ii+ sram rohs-compliant 165-bump bga 400 c 16m x 8 gs81302dt06ge-350 sigmaquad-ii+ sram rohs-compliant 165-bump bga 350 c 16m x 8 gs81302dt06ge-500i sigmaquad-ii+ sram rohs-compliant 165-bump bga 500 i 16m x 8 gs81302dt06ge-450i sigmaquad-ii+ sram rohs-compliant 165-bump bga 450 i 16m x 8 gs81302dt06ge-400i sigmaquad-ii+ sram rohs-compliant 165-bump bga 400 i 16m x 8 gs81302dt06ge-350i sigmaquad-ii+ sram rohs-compliant 165-bump bga 350 i 16m x 9 gs81302dt11e-500 sigmaquad-ii+ sram 165-bump bga 500 c 16m x 9 gs81302dt11e-450 sigmaquad-ii+ sram 165-bump bga 450 c 16m x 9 gs81302dt11e-400 sigmaquad-ii+ sram 165-bump bga 400 c 16m x 9 gs81302dt11e-350 sigmaquad-ii+ sram 165-bump bga 350 c 16m x 9 gs81302dt11e-500i sigmaquad-ii+ sram 165-bump bga 500 i 16m x 9 gs81302dt11e-450i sigmaquad-ii+ sram 165-bump bga 450 i 16m x 9 gs81302dt11e-400i sigmaquad-ii+ sram 165-bump bga 400 i 16m x 9 gs81302dt11e-350i sigmaquad-ii+ sram 165-bump bga 350 i 16m x 9 gs81302dt11ge-500 sigmaquad-ii+ sram rohs-compliant 165-bump bga 500 c 16m x 9 gs81302dt11ge-450 sigmaquad-ii+ sram rohs-compliant 165-bump bga 450 c 16m x 9 gs81302dt11ge-400 sigmaquad-ii+ sram rohs-compliant 165-bump bga 400 c 16m x 9 gs81302dt11ge-350 sigmaquad-ii+ sram rohs-compliant 165-bump bga 350 c 16m x 9 gs81302dt11ge-500i sigmaquad-ii+ sram rohs-compliant 165-bump bga 500 i 16m x 9 gs81302dt11ge-450i sigmaquad-ii+ sram rohs-compliant 165-bump bga 450 i 16m x 9 gs81302dt11ge-400i sigmaquad-ii+ sram rohs-compliant 165-bump bga 400 i notes: 1. customers requiring delivery in tape and reel should add the character ?t? to the end of the part number. example: gs81302dt38e-400t. 2. c = commercial temperature range. i = industrial temperature range.
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 32/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350 16m x 9 gs81302dt11ge-350i sigmaquad-ii+ sram rohs-compliant 165-bump bga 350 i 8m x 18 gs81302dt20e-500 sigmaquad-ii+ sram 165-bump bga 500 c 8m x 18 gs81302dt20e-450 sigmaquad-ii+ sram 165-bump bga 450 c 8m x 18 gs81302dt20e-400 sigmaquad-ii+ sram 165-bump bga 400 c 8m x 18 gs81302dt20e-350 sigmaquad-ii+ sram 165-bump bga 350 c 8m x 18 gs81302dt20e-500i sigmaquad-ii+ sram 165-bump bga 500 i 8m x 18 gs81302dt20e-450i sigmaquad-ii+ sram 165-bump bga 450 i 8m x 18 gs81302dt20e-400i sigmaquad-ii+ sram 165-bump bga 400 i 8m x 18 gs81302dt20e-350i sigmaquad-ii+ sram 165-bump bga 350 i 8m x 18 gs81302dt20ge-500 sigmaquad-ii+ sram rohs-compliant 165-bump bga 500 c 8m x 18 gs81302dt20ge-450 sigmaquad-ii+ sram rohs-compliant 165-bump bga 450 c 8m x 18 gs81302dt20ge-400 sigmaquad-ii+ sram rohs-compliant 165-bump bga 400 c 8m x 18 gs81302dt20ge-350 sigmaquad-ii+ sram rohs-compliant 165-bump bga 350 c 8m x 18 gs81302dt20ge-500i sigmaquad-ii+ sram rohs-compliant 165-bump bga 500 i 8m x 18 gs81302dt20ge-450i sigmaquad-ii+ sram rohs-compliant 165-bump bga 450 i 8m x 18 gs81302dt20ge-400i sigmaquad-ii+ sram rohs-compliant 165-bump bga 400 i 8m x 18 gs81302dt20ge-350i sigmaquad-ii+ sram rohs-compliant 165-bump bga 350 i 4m x 36 gs81302dt38e-500 sigmaquad-ii+ sram 165-bump bga 500 c 4m x 36 gs81302dt38e-450 sigmaquad-ii+ sram 165-bump bga 450 c 4m x 36 gs81302dt38e-400 sigmaquad-ii+ sram 165-bump bga 400 c 4m x 36 gs81302dt38e-350 sigmaquad-ii+ sram 165-bump bga 350 c 4m x 36 gs81302dt38e-500i sigmaquad-ii+ sram 165-bump bga 500 i 4m x 36 gs81302dt38e-450i sigmaquad-ii+ sram 165-bump bga 450 i 4m x 36 gs81302dt38e-400i sigmaquad-ii+ sram 165-bump bga 400 i 4m x 36 gs81302dt38e-350i sigmaquad-ii+ sram 165-bump bga 350 i 4m x 36 gs81302dt38ge-500 sigmaquad-ii+ sram rohs-compliant 165-bump bga 500 c 4m x 36 GS81302DT38GE-450 sigmaquad-ii+ sram rohs-compliant 165-bump bga 450 c 4m x 36 gs81302dt38ge-400 sigmaquad-ii+ sram rohs-compliant 165-bump bga 400 c 4m x 36 gs81302dt38ge-350 sigmaquad-ii+ sram rohs-compliant 165-bump bga 350 c 4m x 36 gs81302dt38ge-500i sigmaquad-ii+ sram rohs-compliant 165-bump bga 500 i 4m x 36 GS81302DT38GE-450i sigmaquad-ii+ sram rohs-compliant 165-bump bga 450 i ordering information gsi sigmaquad-ii+ sram org part number 1 type package speed (mhz) t j 2 notes: 1. customers requiring delivery in tape and reel should add the character ?t? to the end of the part number. example: gs81302dt38e-400t. 2. c = commercial temperature range. i = industrial temperature range.
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00a 7/2011 33/33 ? 2011, gsi technology gs81302dt06/11/20/38e -500/450/400/350 4m x 36 gs81302dt38ge-400i sigmaquad-ii+ sram rohs-compliant 165-bump bga 400 i 4m x 36 gs81302dt38e-350i sigmaquad-ii+ sram rohs-compliant 165-bump bga 350 i sigmaquad-ii+ sram revision history file name format/content description of changes 81302dt2038e_r1 ? creation of datasheet ? (rev1.00a: added missing x18/x36 idd numbers) ordering information gsi sigmaquad-ii+ sram org part number 1 type package speed (mhz) t j 2 notes: 1. customers requiring delivery in tape and reel should add the character ?t? to the end of the part number. example: gs81302dt38e-400t. 2. c = commercial temperature range. i = industrial temperature range.

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